DDR2 SDRAM Memory

DDR2 was the second generation of double data rate SDRAM and it provided a significant increase in performance.

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What is SDRAM memory SDRAM architecture SDRAM timing & control DDR / DDR1 SDRAM DDR2 SDRAM DDR3 SDRAM DDR4 SDRAM JEDEC 79 Standard

Memory types: Memory types & technologies DRAM EEPROM Flash FRAM MRAM Phase change memory SDRAM SRAM

DDR2 SDRAM was the second generation of double data rate SDRAM. It could operate the external bus twice as fast as its predecessor, giving a major boost to overall system performance.

DDR2 SDRAM memory was first introduced in 2003. Initially the new DDR2 SDRAM memory did not outperform the previous DDR1 generation of SDRAM as a result of a latency problem.

Later the issue was resolved and when the new memories were launched in 2004 they were easily able to out perform the DDR1 memories.

DDR2 SDRAM basics

DDR2 memory is more complicated than its predecessor. The memory cells are activated in a way that enables them to operate with an external bus. As with DDR, DDR2 transfers data at twice the clock speed by transferring data on the rising and falling clock edges, but the bus is clocked at twice the speed of that for DDR. This increase in clock speed is achieved by using a number of interface improvements including what are termed pre-fetch buffers and off-chip drivers. The problem with DDR2 is that the buffers introduce a latency which is twice that of DDR, requiring a doubling of the bus speed to counteract the latency.

The improvements provided by DDR2 come at a cost. As a result of the additional circuitry and the more exacting packaging requirements, DDR2 chips are more expensive than their DDR, or straight SDRAM predecessors.

One of the changes that DDR2 SDRAM has implemented is a reduction in the supply or operating voltage. It runs with a power line voltage of 1.8 volts against 2.5 volts for DDR SDRAM. Although this represents a reduction in voltage of 72%, this would reduce the power consumed by approximately 50% for the same circuit.

Not only is the power consumption reduced by the lower operating voltage, but it also improves the operating speed. For the same slew rate, the chip is able to transition between the high and low states faster - there is less of a voltage swing required in absolute terms.

A further improvement is that the data strobe can be programmed to operate in a differential mode. Using a differential signal reduces noise, crosstalk, dynamic power consumption and electromagnetic interference.

DDR2 SDRAM data rates and clock speeds
DDR2 SDRAM Type	Data Rate Mb/s/pin	Memory Clock Speed (MHz)
DDR2-400	400	200
DDR2-533	533	266
DDR2-667	667	333
DDR2-800	800	400
DDR2-1066	1066	533

DDR2 SDRAM signal integrity

With the speeds of the signals for DDR2 SDRAM being much higher than previous versions of SDRAM, signal integrity becomes an increasingly important issue. There are a number of main points associated with DDR2 signal integrity:

PCB layout: To ensure that there are no issues resulting from the signal integrity for the DDR2 SDRAM chips PCB layout precautions must be adopted because the PCB tracks react as transmission lines with the very high frequencies being carried.

The lines must be kept short and they must be properly terminated to prevent reflections causing multiple edges.
Line directions: For DDR2 SDRAM, the address, clock and command signals are relatively straightforward because these signals are only unidirectional - this simplifies the terminating techniques, enabling the lines to be terminated on the circuit board.

However the data signals and strobe lines are bi-directional - they are driven by the memory controller during a write operation, and by the DDR2 SDRAM during read operations.

In addition to this multiple DDR2 SDRAM chips are connected to the same data and strobe lines. Not only this, but multiple DDR2 SDRAMs can be on the same or even different DIMMs in an overall memory system. This means that great care must be taken in ensuring signal integrity is maintained across the whole memory system.
On-die termination: To ensure that the correct termination is applied for the system, the on-die termination is controlled by the memory controller hub. The On-Die Termination, ODT, process enables the line termination to be much more closely adapted to the real requirements. This improves the signal integrity, and increases the voltage margins, reduces slew rate, and overshoot. This all results in reduced inter-symbol interference and reduces data errors.
Additive latency: A further feature that has been introduced is known as additive latency. This provides the DDR2 SDRAM controller hub with the flexibility to send read or write commands sooner after the Activate command that previously possible. This improves the memory data throughput.

DDR2 SDRAM enabled a significant increase in performance compared to previous forms of SDRAM. The increased speed of operation made a significant increase in performance of the whole system, along much faster overall processing.