D-type frequency divider circuit
- information and circui for a logic D-type flip flop electronic circuit to provide a frequency division of two.
Logic / Digital Design Includes:
Logic gate types
Logic truth table
How to convert NAND / NOR gates with inverters
Exclusive OR, XOR
RS Flip-Flop
Edge triggered RS Flip-Flop
Programmable inverter
D-type frequency divider
The D-type logic flip flop is a very versatile circuit. It can be used in many areas where an edge triggered circuit is needed. In one application this logic or digital circuit provides a very easy method of dividing an incoming pulse train by a factor of two.
The divide by two circuit employs one logic d-type element. Simply by entering the pulse train into the clock circuit, and connecting the Qbar output to the D input, the output can then be taken from the Q connection on the D-type.
D-type frequency divide by two circuit
The circuit operates in a simple way. The incoming pulse train acts as a clock for the device, and the data that is on the D input is then clocked through to the output. To see exactly how the circuit works it is worth examining what happens at each stage of the waveforms shown below. Take the situation when the Q output is a level '1'. This means that the Qbar output will be at '0'. This data is clocked through to the output Q on the next positive going edge from the incoming pulse train on the clock input. At this point the output changes from a '1' to a '0'. At the next positive going clock pulse, the data on the Qbar output is again clocked through. As it is now a '1' (opposite to the Q output), this is transferred to the output, and the output again changes state.
Division by two
It can be seen that the output of the circuit only changes state on the positive going edges of the incoming pulse clock stream. Each positive edge occurs once every cycle, but as the output of the D type requires two changes to complete a cycle, it means that the output from the D-type circuit changes at half the rate of the incoming pulse train. In other words it ahs been divided by two.
There are some precautions when using this type of circuit. The first is that the pulse train should have sharp edges. If the rising edges are insufficiently sharp then there may be problems with the circuit operating as it should. If this is the case, then the problem can be easily overcome by simply placing an inverter before the clock input. This has the effect of sharpening the edges on the incoming signal.
Previous page Next page Written by Ian Poole .
Experienced electronics engineer and author.
More Digital Logic and Embedded Topics:
FPGA programming
Embedded systems
How a computer works
Logic circuit design basics
Logic / circuit design guidelines
Return to Digital / Logic / Processing menu . . .