cJTAG IEEE 1149.7 Standard

- a summary, overview or tutorial of the basics of Compact JTAG or cJTAG defined under IEEE 1149.7 standard for boundary scan testing.

Boundary Scan JTAG Includes:
What is Boundary Scan / JTAG Boundary scan description language, BSDL Design for test with boundary scan JTAG Spec & IEEE 1149 Standard JTAG TAP & connector IEEE 1149.6 (AC coupled JTAG) Compact JTAG cJTAG IEEE 1149.7 IJTAG, IEEE 1687

The IEE 1149.7 standard is a new standard also referred to as Compact JTAG or cJTAG that has been developed to meet the ever increasing needs of testing modern electronics boards and systems. The original JTAG standard provided a real leap forwards in testing, but as many designs moved away from conventional printed circuit boards to multi-chip modules, stacked die packages,and further testing and debug was required, including under power down and low power operation, an addition to the original JTAG standard was needed.

The resulting IEEE 1149.7 standard builds on the existing JTAG standard to meet many of the new requirements. The new IEEE 1149.7 standard does not replace the older IEEE 1149.1 JTAG standard, but its aim is to enable this basic JTAG test technique to be used in many of the new high density boards where greater flexibility and further functionality is required to provide sufficient test coverage. These additional facilities are available on Compact JTAG / IEEE 1149.7 while still providing backwards compatibility.

Equipment conforming to the IEEE 1149.7 cJTAG or Compact JTAG standard is now available from a variety of vendors and it is anticipated that its use will greatly increase over the coming years.

IEEE 1149.7 cJTAG basics

One of the key elements of Compact JTAG is that the IEEE 1149.7 standard defines a new Test Access Port (TAP) known as TAP.7. This extends the functionality of the Test Access Port of the original JTAG standard (TAP.1) in several ways.

One of the main elements is that the focus of JTAG testing has been broadened somewhat. The original IEEE 1149.1 standard was developed as a means of testing board level interconnections, but the new IEEE 1149.7 standard incorporates additional features to bring additional test facilities. It provides power management facilities; supports increased chip integration; application debug; and device programming.

In view of the fact that not all facilities will be required for all testers and applications, the IEEE 1149.7 features are grouped into six classes which are progressively graded. Each class is a superset of all the lower classes. Classes T0 to T3 extend the original IEEE 1149.1 standard and enable greater functionality. Classes T4 and T5 are focussed on the two pin system operation rather than the four required for the original JTAG system.

cJTAG Class	Details
Class T0	This is the basic class for Compact JTAG testing. It maintains strict compliance to the original IEEE 1149.1 but in addition to this it also allows multiple Test Access Ports on a single chip.
Class T1	This class provides the class 0 facilities as well as providing support for the 1149.7 command protocol, the generation of functional and test resets, and power control.
Class T2	The Class 2 functionality additionally provides the ability to bypass the system test logic on each IC. This results in a 1-bit path being created for Instruction Register and Data Register scans.
Class T3	This class adds the facility to use TAP.7 controllers in a 4-wire star topology.
Class T4	This class adds support for advanced scan protocols and 2-pin operation where all the signalling is accomplished using only the TMS and TCK pins. The TDO and TDI lines can be removed if required.
Class T5	Class 5 provides the maximum functionality within IEEE 1149.7. It adds support for up to 2 data channels for non-scan data transfers. These can be used for application specific debug and instrumentation applications.

cJTAG, IEEE 1149.7 Summary

Although the Compact JTAG or cJTAG standard specified under IEEE 1149.7 only uses two pins for the TAP rather than the four pins used for the original IEEE 1149.1 standard, it is still able to provide additional functionality. These enhancements enable System on Chip pin counts to be reduced and it provides a standardised format for power saving operating conditions. As a result, the IEEE 1149.7 standard will enable JTAG style testing to be undertaken on many new designs more easily than it would have been possible using the older IEEE 1149.1 standard.